(6500-1020) Staff Verification Engineer (Ethernet)

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

The successful candidate will contribute to the verification and validation of FPGA cores and related ASIC subsystems implemented in modern FPGA technology nodes (16nm/7nm and below).

Responsibilities include the following:

• Verify ASIC logic subsystems developed for high-speed networking and data center applications for inclusion in modern FPGAs, with focus on Ethernet and packet transport subsystems
• Define and review verification plans and tests in collaboration with the design team
• Develop automated processes for block- and system-level development and verification
• Implement functional coverage and enhance the testbench to ensure coverage closure
• Contribute to customer deliverables related to verification and device modeling
• Collaborate with internal and external team members on architectural decisions, development flows and methodologies
• Contribute to device bring-up and Post-Silicon validation

• Strong knowledge of Verilog, SystemVerilog, and Object-Oriented Programming
• Experience with modern Pre-Silicon verification techniques, especially including SystemVerilog, UVM, constraint-random and functional coverage methodologies
• Complete understanding of verification life cycle and ability to create comprehensive verification plans
• Experience verifying Ethernet controllers, packet subsystems, and SerDes
• Knowledge of types of PHY training algorithms, tester algorithms as well as diagnostic and debug mechanisms
• Experience with scripting languages such as Python, Tcl, or Perl
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
• Strong technical writing and communication (verbal) skills

Additional skills considered a bonus:

• Experience with mixed signal verification methodology in the context of PHY verification
• Knowledge and familiarity with FPGA design flows, including FPGA synthesis, place and route, timing closure, and debug tools

• A minimum of 5+ years experience
• Bachelor or Master’s degree in Computer or Electrical Engineering