Verification Engineer

POSITION SUMMARY

Title: Design Verification Engineer

Location: San Jose, CA

Duration: 6+ Months

QUALIFICATIONS:

Skills/Experience • Mandatory Experience

• Writing and maintaining test plans o Creating and maintaining UVM testbenches
• Created a module testbench from scratch
• Written Cover points, Assertions (SVA) and closed coverage
• Knowledge of standard bus protocols such as AHB, AXI, etc.

Desirable Experience

• Scripting and test automation for regression
• Experience with PCIe/NVMe and/or ONFI
• Experience with SSD architecture

Education Requirements

• BS/MS in EE/CE, plus 5+ years of Design Verification experience
• Familiarity with ASIC, Computer and Embedded Systems Architectures
• Excellent oral and written communication skills with people at all levels, a must.
• Team player, with excellent debugging skills

Regards,

Paige Sampson

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