Sunnyvale, CA

Senior Validation Engineer

Understand the SOC architecture, work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop the validation software content and silicon bring up plan.Use silicon debug hooks to measure power/performance/coverage and other Key metrics.

* 8+ years Hardware Engineering experience or related work experience.

* Basics of Multicore/Multiprocessor architecture
* Good knowledge of RISC-V architecture, PCIe subsystem and DDR memory system architecture
* Weakly ordered memory model/pipelining of memory systems/memory barriers
* Software development of multi-threaded applications
* C language expertise for low level programming, Assembly language for any processor, C-assembly interworking
* Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism.
* Exposure to working on emulation/pre-silicon environment is added advantage
* Using JTAG based debuggers, compilers/linkers
* Should have good exposure to software development life cycle.
* Exposure to SoC architecture paradigms interconnects, power management,
* Software development for silicon enablement, silicon validation
* Bring-up of hardware-software solution on FPGA/emulation platforms and on first silicon SOC designs
* Software for power/performance
* Top level of ASIC design methodology is a plus
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